NoMaY-jp

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February 24, 2023 Commented Hello support team, Are there any new topics? The following thread was closed with the status of `Verified Answer`. Is there any migration plan of FIT and RX SmartConfigurator due to future deprecation of GNURX's Automatic interrupt vector entry generation feature? https://community.renesas.com/mcu-mpu/rx/f/rx-forum/29337/is-there-any-migration-plan-of-fit-and-rx-smartconfigurator-due-to-future-deprecation-of-gnurx-s-automatic-interrupt-vector-entry-generation-feature Best regards, NoMaY

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January 29, 2023 Asked LLVM for Renesas RL78 10.0.0.202212 can’t assemble the src/smc_gen/r_bsp/mcu/all/start.S while 10.0.0.202209 can do it

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December 9, 2022 Commented Hello support team, Thank you for improving this in the GCC 8.3.0.202204-GNURX. I get the following code even in the CASE B. CASE B: with -mdfp rx-elf-gcc -std=gnu99 -O3 -misa=v3 -mdfpu -mtfu=intrinsic,mathlib -Wa,-adln=rxv3_tfu_sinf_cosf.lst -c rxv3_tfu_sinf_cosf.c 1 .file "rxv3_tfu_sinf_cosf.c" 2 .section P,"ax" 3 .global _rot 5 _rot: 6 0000 7E A7 push.l r7 7 0002 FB EE 14 14 08 mov.L #0x81414, r14 8 0007 E3 E1 mov.L r1, [r14] 9 0009 FB 4E 10 14 08 mov.L #0x81410, r4 10 000e EC EF mov.L [r14], r15 11 0010 A8 2F mov.L 4[r2], r7 12 0012 A0 49 mov.L r1, 4[r4] 13 0014 EC 45 mov.L [r4], r5 14 0016 FC 8F 7F fmul r7, r15 15 0019 EC 27 mov.L [r2], r7 16 001b FC 8F 75 fmul r7, r5 17 001e FC 83 F5 fsub r15, r5 18 0021 E3 35 mov.L r5, [r3] 19 0023 E3 E1 mov.L r1, [r14] 20 0025 EC EE mov.L [r14], r14 21 0027 EC 2F mov.L [r2], r15 22 0029 A0 49 mov.L r1, 4[r4] 23 002b EC 45 mov.L [r4], r5 24 002d A8 2C mov.L 4[r2], r4 25 002f FC 8F FE fmul r15, r14 26 0032 FC 8F 45 fmul r4, r5 27 0035 FC 8B E5 fadd r14, r5 28 0038 A0 3D mov.L r5, 4[r3] 29 003a 3F 77 01 rtsd #4, r7-r7 31 .ident "GCC: (GCC_Build_20221126) 8.3.0.202204-GNURX 20190222" In the Release Notes of the GCC 8.3.0.202204-GNURX: 2. [Improvement] Negated floats getting promoted to double In previous releases, negation of floats resulted in their promotion to double, generating sub-optimal code if doubles were represented on 8 bytes. In the current release of the compiler, promotion will no longer happen when negating floats. Best regards, NoMaY P.S. I notice that the two generated codes are slightly different. (It isn't a problem.) CASE A: without -mdfpu rx-elf-gcc -std=gnu99 -O3 -misa=v3 -mtfu=intrinsic,mathlib -Wa,-adln=rxv3_tfu_sinf_cosf.lst -c rxv3_tfu_sinf_cosf.c 1 .file "rxv3_tfu_sinf_cosf.c" 2 .section P,"ax" 3 .global _rot 5 _rot: 6 0000 7E A7 push.l r7 7 0002 FB FE 14 14 08 mov.L #0x81414, r15 8 0007 E3 F1 mov.L r1, [r15] 9 0009 FB EE 10 14 08 mov.L #0x81410, r14 10 000e EC F4 mov.L [r15], r4 11 0010 A8 2F mov.L 4[r2], r7 12 0012 E7 E1 01 mov.L r1, 4[r14] 13 0015 EC E5 mov.L [r14], r5 14 0017 70 44 00 00 00 80 add #-2147483648, r4 <-- HERE 15 001d FC 8F 74 fmul r7, r4 16 0020 EC 27 mov.L [r2], r7 17 0022 FC 8F 75 fmul r7, r5 18 0025 FC 8B 45 fadd r4, r5 <-- HERE 19 0028 E3 35 mov.L r5, [r3] 20 002a E3 F1 mov.L r1, [r15] 21 002c EC F4 mov.L [r15], r4 22 002e EC 2F mov.L [r2], r15 23 0030 E7 E1 01 mov.L r1, 4[r14] 24 0033 EC E5 mov.L [r14], r5 25 0035 A8 2A mov.L 4[r2], r2 26 0037 FC 8F F4 fmul r15, r4 27 003a FC 8F 25 fmul r2, r5 28 003d FC 8B 45 fadd r4, r5 29 0040 A0 3D mov.L r5, 4[r3] 30 0042 3F 77 01 rtsd #4, r7-r7 32 .ident "GCC: (GCC_Build_20221126) 8.3.0.202204-GNURX 20190222" CASE B: with -mdfp rx-elf-gcc -std=gnu99 -O3 -misa=v3 -mdfpu -mtfu=intrinsic,mathlib -Wa,-adln=rxv3_tfu_sinf_cosf.lst -c rxv3_tfu_sinf_cosf.c 1 .file "rxv3_tfu_sinf_cosf.c" 2 .section P,"ax" 3 .global _rot 5 _rot: 6 0000 7E A7 push.l r7 7 0002 FB EE 14 14 08 mov.L #0x81414, r14 8 0007 E3 E1 mov.L r1, [r14] 9 0009 FB 4E 10 14 08 mov.L #0x81410, r4 10 000e EC EF mov.L [r14], r15 11 0010 A8 2F mov.L 4[r2], r7 12 0012 A0 49 mov.L r1, 4[r4] 13 0014 EC 45 mov.L [r4], r5 14 0016 FC 8F 7F fmul r7, r15 15 0019 EC 27 mov.L [r2], r7 16 001b FC 8F 75 fmul r7, r5 17 001e FC 83 F5 fsub r15, r5 <-- HERE 18 0021 E3 35 mov.L r5, [r3] 19 0023 E3 E1 mov.L r1, [r14] 20 0025 EC EE mov.L [r14], r14 21 0027 EC 2F mov.L [r2], r15 22 0029 A0 49 mov.L r1, 4[r4] 23 002b EC 45 mov.L [r4], r5 24 002d A8 2C mov.L 4[r2], r4 25 002f FC 8F FE fmul r15, r14 26 0032 FC 8F 45 fmul r4, r5 27 0035 FC 8B E5 fadd r14, r5 28 0038 A0 3D mov.L r5, 4[r3] 29 003a 3F 77 01 rtsd #4, r7-r7 31 .ident "GCC: (GCC_Build_20221126) 8.3.0.202204-GNURX 20190222" Best regards, NoMaY

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December 9, 2022 Commented Hello support team, Thank you for improving this in the GCC 8.3.0.202204-GNURX. And I hope future improvement for the case that such push/pop sequence is not necessary. (I understand/remember that `optimizations are always in the scope of future releases`.) In the Release Notes of the GCC 8.3.0.202204-GNURX: 1. [Improvement] DCMR register not getting saved/restored on function entry/exit In the current release, the DCMR register will be saved on function entry and restored on function exit. Best regards, NoMaY

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December 7, 2022 Commented Hello support team, I have posted my idea to the Renesas Rulz English Forum. reply - Is there any migration plan of FIT and RX SmartConfigurator due to future deprecation of GNURX's Automatic interrupt vector entry generation feature? https://community.renesas.com/mcu-mpu/rx/f/rx-forum/29337/is-there-any-migration-plan-of-fit-and-rx-smartconfigurator-due-to-future-deprecation-of-gnurx-s-automatic-interrupt-vector-entry-generation-feature/100827#100827 Best regards, NoMaY

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0 January 29, 2023 0 answers

LLVM for Renesas RL78 10.0.0.202212 can’t assemble the src/smc_gen/r_bsp/mcu/all/start.S while 10.0.0.202209 can do it

0 February 24, 2023 0 answers

Please don’t remove Automatic interrupt vector entry generation feature because RX SmartConfigurator strongly depends on it and there is an easy workaround

0 December 9, 2022 0 answers

Difference of generated code regarding GNURX for RXv3 `float` operation between with and without -mdfpu (code – 2022/10/26)

0 December 1, 2022 0 answers

Difference of generated code regarding GNURX for RXv3 sqrtf(x) using -mrxv2-fsqrt between with and without -mdfpu (code – 2022/10/25)

0 October 26, 2022 0 answers

Wrong generated code regarding GNURX for RXv3 TFU mathlib hypotf(x, y) (code – 2022/10/24)

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